When forming a DC-DC converter, in general, an inductor is attached to a power source IC which has been supplied as an external part. In recent years, downsizing of a power source circuit is also demanded and it is desired to accommodate the inductor within the power source IC. In order to accommodate the inductor within the power source IC, the inductor is downsized, however, if the inductor is downsized, the value of inductance is also reduced. If the inductance value of the inductor and the capacitance value are reduced, the output voltage ripple (noise) increases. In order to reduce the inductance value and the capacitance value while satisfying the specifications on the output voltage ripple (noise) of the DC-DC converter, the switching frequency is raised (increased). However, if the switching frequency is raised, then an electric power loss accompanying the charge and discharge operation of the capacitor increases and efficiency is reduced.
As described above, in the DC-DC converter, coexistence of high efficiency and downsizing creates a technical problem.
It is known to reduce the electric power loss accompanying switching to 1/S by vertically stacking transistors scaled (downsized) with a scaling factor S in S stages. However, if multiple output stages are stacked, then the capacitance value of the bias capacitor increases in order to suppress fluctuations of the bias voltage and it is also difficult to implement a vertical stack of three or more stages because of difficulty in designing the driver circuit.